1. Field of the Invention
The present invention relates to electronic interconnect structures and, more particularly, to methods and structures for making the microstructure in metallization more effective and reliable as an electronic interconnect.
2. Background and Related Art
It is well known that the microstructure in metallization plays one of the more critical roles in dictating the reliability of electronic interconnects, including the electromigration and stress voiding behaviors. For example, it is known that large columnar or bamboo-type grain structures in copper and aluminum interconnects, with grain boundaries across the interconnect film thickness and line width, are the most favorable grain structures in terms of electromigration stability and reliability. This is thought to be due to the fact that grain boundaries are the fast diffusion paths during electromigration, and having grain boundaries oriented perpendicular to the electromigration flux significantly slows down the mass transport.
It is known that desirable grain structure, and particularly grain growth, can be achieved by annealing the metallization during electronic device fabrication. For example, annealing electroplated copper (Cu) before standard chemical-mechanical polishing (CMP) of the device to planarize the copper, typically may be performed at 100° C. for around an hour. Such annealing promotes a recrystallization and grain growth in the Cu structure, wherein grain growth lowers energy by reducing grain boundary area, while recrystallization lowers energy by eliminating mechanically strained grains.
Since recrystallization and grain growth are both thermally activated processes involving atomic diffusion, it is desirable to anneal at higher temperatures so as to reduce the anneal process time. However, it has been found that high temperature anneal results in reliability exposure due to stress voiding. In this regard, it is noted that the impact of annealing the metal film on stress voiding reliability is due to thermal stress generation and relaxation. It is understood that because of the mismatch in thermal expansion coefficients between the metal film and the surrounding dielectric structure and substrate, significant thermal stress is induced from temperature change.
Accordingly, when annealing a metal at elevated temperatures, such as around 300° C. and above, the metal film is subjected to compressive stress which tends to relax by atomic diffusion on the surface and grain boundaries, and thus forms hillocks on the free surface. As a result, it is understood that the metal film is subjected to large tensile stress when it is cooled to lower temperatures resulting in stress voids at device operating temperatures.
Neither the hillock formation on the free surface nor the stress voids are desirable in terms of creating a reliable and effective interconnect structure. It is, therefore, important to reduce the stress relaxation at elevated annealing temperatures so that microstructure stabilization in the metallization layer can be accelerated without compromising stress voiding reliability.